中国邮电高校学报(英文) ›› 2010, Vol. 17 ›› Issue (2): 109-115.doi: 10.1016/S1005-8885(09)60455-6

• Artificial Intelligence • 上一篇    下一篇

Reconfigurable Design and Implementation of the MD6 Hash Function

高献伟   

  1. 北京电子科技学院
  • 收稿日期:2009-03-31 修回日期:2010-02-17 出版日期:2010-04-30 发布日期:2010-06-01
  • 通讯作者: 高献伟 E-mail:gaoxianwei@besti.edu.cn
  • 基金资助:

    国家级.国家“863计划”项目

Reconfigurable Design and Implementation of the MD6 Hash Function

  • Received:2009-03-31 Revised:2010-02-17 Online:2010-04-30 Published:2010-06-01

摘要:

Efficient reconfigurable FPGA architectures for the MD6-224/256/384/512 hash algorithm are proposed in this work. The basic iterative compact design requires 923 ALMs, achieves a throughput ranges from 225 to 394 Mbps at the maximum frequency of 198MHz; the 32-step-unrolled high-throughput design requires 7 090 ALMs, achieves a throughput ranges from 5 776 to 9 490 Mbps at the maximum frequency of 173MHz. The implementation results show that high flexibility and efficient FPGA implementation of the MD6 hash function is achieved.

关键词:

SHA-3, md6, reconfigurable, iterative, loop-unrolling

Abstract:

Efficient reconfigurable FPGA architectures for the MD6-224/256/384/512 hash algorithm are proposed in this work. The basic iterative compact design requires 923 ALMs, achieves a throughput ranges from 225 to 394 Mbps at the maximum frequency of 198MHz; the 32-step-unrolled high-throughput design requires 7 090 ALMs, achieves a throughput ranges from 5 776 to 9 490 Mbps at the maximum frequency of 173MHz. The implementation results show that high flexibility and efficient FPGA implementation of the MD6 hash function is achieved.

Key words:

SHA-3, md6, reconfigurable, iterative, loop-unrolling